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ISL97653A
Data Sheet December 6, 2007 FN6367.0
5-Channel Integrated LCD Supply
The ISL97653A represents a fully integrated supply IC for LCD-TV applications. With an input operating range of 4V to 14V, both commonly used LCD-TV input supplies, 5V and 12V, are supported. An AVDD supply up to 20V is generated by a high-performance PWM BOOST converter with an integrated 4.4A FET. VON is generated using an integrated charge pump with on-chip diodes and can be modulated using an on-chip VON slice control circuit. VOFF is generated using an integrated charge pump controller. Additionally, the chip allows for two logic supplies. A buck regulator with an included 2.5A high side switch is used for the main logic output and an internal LDO controller can be used to generate a second logic LDO output. To facilitate production test, an integrated HVS circuit is included which can provide high voltage stress of the LCD panel. An on-board temperature sensor is also provided for system thermal management control. The ISL97653A is packaged in a 40 Ld 6mmx6mm QFN package and is specified for operation over the -40C to +105C temperature range.
Features
* 5V to 14V Input Supply * Integrated 4.4A Boost Converter * Integrated VON Charge Pump and VON Slice Circuit * Integrated VOFF Charge Pump Output * Integrated 2.5A Buck Converter * LDO Controller for an Additional Logic Supply * High Voltage Stress (HVS) Test Mode * Thermal Shutdown * 40 Ld QFN (6mmx6mm) Package * Pb-Free (RoHS Compliant)
Applications
* LCD-TVs * Industrial/Medical LCD Displays
Pinout
ISL97653A 40 LD 6X6 QFN TOP VIEW
LDO-CTL LDO-FB PGND2 PGND1 32 AGND PVIN1 TEMP 31 30 COMP 29 FBB 28 RSET 27 HVS 26 EN 25 CDEL 24 CTL 23 DRN 22 COM 21 POUT 11 FBN 12 SUPN 13 NOUT 14 PGND5 15 C1P 16 C1N 17 C2P 18 C2N 19 SUPP 20 FBP PROT
Ordering Information
PART NUMBER (Note) ISL97653AIRZ ISL97653AIRZ-T* PART MARKING ISL97653A ISL97653A PACKAGE (Pb-Free) 40 Ld 6X6 QFN 40 Ld 6X6 QFN Tape and Reel 40 Ld 6X6 QFN Tape and Reel PKG. DWG. # L40.6X6 L40.6X6 L40.6X6
LXL1 LXL2 PGND3 PGND4 CM2 FBL VL VREF 3 4 5 6 7 8 9 10 PVIN2 CB 1 2
LX2 35
40
39
38
37
36
34
LX1
33
ISL97653AIRZ-TK* ISL97653A
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97653A
Absolute Maximum Ratings (TA = +25C)
Maximum Pin Voltages, all pins except below . . . . . . . . . . . . . . 6.5V LX1, LX2, SUPP, SUPN, NOUT, PROT, C1N, C2N . . . . . . . . .24V PVIN1, PVIN2, LXL1, LXL2 . . . . . . . . . . . . . . . . . . . . . . . . . 16.8V EN, CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V DRN, POUT, COM, C1P, C2P. . . . . . . . . . . . . . . . . . . . . . . . . .33V CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21V
Thermal Information
Operating Ambient Temperature Range . . . . . . . . -40C to +105C Operating Junction Temperature . . . . . . . . . . . . . . -40C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 4V to 14V Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2x10F Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . . . . . . . +20V Output Capacitance, COUT . . . . . . . . . . . . . . . . . . . . . . . . . . 3x22F Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3H-10H VON Output Range, VON . . . . . . . . . . . . . . . . . . . . . . +15V to +30V VOFF Output Range, VOFF . . . . . . . . . . . . . . . . . . . . . . . -15V to -5V Logic Output Voltage Range, VLOGIC . . . . . . . . . . . . +1.5V to +3.3V Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3H to 10H
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
Electrical Specifications
PARAMETER SUPPLY PINS VIN IS
VIN = 12V, VBOOST = VSUPN = VSUPP = 15V, VON = 25V, VOFF = -8V, over temperature from -40C to +105C, unless otherwise stated. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Supply Voltage Quiescent Current Enabled, no switching Disabled
4 4 2.7 580 TA = +25C 1.190 1.187 680 1.215 1.215 3.55 3.0 150 20
14 5 3.5 780 1.240 1.243 3.7 3.2
V mA mA kHz V V V V C C
FSW VREF
Switching Frequency Reference Voltage
VLOR VLOF
Undervoltage Lockout Threshold Undervoltage Lockout Threshold Thermal Shutdown Thermal Shutdown Hysteresis
VL rising VL falling Temperature rising
3.4 2.9
LOGIC SIGNALS HVS, EN, CTL Logic Input High Logic Input Low Pull-down Resistance HVS, RSET RSET IRSET AVDD BOOST DLIM Min Duty Cycle Max Duty Cycle VBOOST EFFBOOST VFB Boost Output Range Boost Efficiency Boost Feedback Voltage VIN = 12V, VBOOST = 15V TA = +25C 1.203 1.198 8.5 90 20 90+ 1.215 1.215 1.227 1.232 12 % % V % V V RSET Pull-down Resistance RSET Leakage Current HVS = HIGH HVS = LOW, VRSET = 1.2V 200 0.4 A 130 174 2.0 0.4 215 V V k
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ISL97653A
Electrical Specifications
PARAMETER IBOOST RDSON-BOOST VBOOST/VIN VBOOST/IOUT LOGIC BUCK EFFBUCK IBUCK RDSON-BUCK VLDO/IOUT VFL Buck Efficiency Buck FET Current Limit Switch On Resistance Load Regulation - Buck Feedback Voltage Load 100mA to 500mA TA = +25C 1.195 1.189 VON CHARGE PUMP ILoad_PCP_min External Load Driving Capability VON = 24V (2X Charge Pump) VON = 28V (3X Charge Pump) VFBP Feedback Voltage, ION = 1mA TA = +25C 40 40 1.195 1.189 RON (VSUP_SW) RON (C1/2-)H RON (C1/2-)L VON Load Reg V(diode) VOFF CHARGE PUMP ILoad_NCP_min VFBN External Load Driving Capability Feedback Voltage, IOFF = 10mA SUPN>13.5V VOFF=-8V TA = +25C 100 0.173 0.171 RON (NOUT)H RON (NOUT)L VOFF Load Reg LDO Controller IDRVP LDO-FB Sink Current VFBP = 1.1V, VLDO_CTL = 10V 12 1.191 1.189 FAULT DETECTION THRESHOLDS T_off Vth_AVDD(FBB) Thermal Shut-Down (latched and reset Temperature rising by power cycle or EN cycle) AVDD Boost Short Detection V(FBB) falling less than 150 0.9 C V 15 1.215 1.215 1.239 1.241 mA V V High-Side Driver ON Resistance at NOUT Low-Side Driver ON Resistance at NOUT VOFF Output Load Reg I(NOUT) = +60mA I(NOUT) = -60mA IOFF = 10mA to 100mA, TA = +25C 120 0.203 0.203 0.233 0.235 10 5 2.4 mA V V % ON Resistance of VSUP Input Switch High-Side Driver ON Resistance at C1- and C2Low-Side Driver ON Resistance at C1- and C2VON Output Load Regulation I(switch) = +40mA I(C1/2-) = +40mA I(C1/2-) = -40mA ION = 10mA to 40mA 700 4 1.215 1.215 10 1.235 1.241 17 30 10 +1 800 mA mA V V % mV VIN = 5V, VLOGIC = 3.3V 1.9 150 0.5 1.215 1.215 90+ 4.0 210 1 1.235 1.241 % A m % V V VIN = 12V, VBOOST = VSUPN = VSUPP = 15V, VON = 25V, VOFF = -8V, over temperature from -40C to +105C, unless otherwise stated. (Continued) DESCRIPTION Boost FET Current Limit Switch On Resistance Line Regulation - Boost Load Regulation - Boost Load 100mA to 200mA CONDITIONS MIN 3.7 TYP 4.4 93 0.08 0.004 MAX 4.95 200 0.15 1 UNIT A m % %
Internal Schottky Diode Forward Voltage I(diode) = +40mA Drop
Feedback Voltage w/transistor load 1mA TA = +25C
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Electrical Specifications
PARAMETER Vth_POUT (FBP) Vth_NOUT (FBN) VIN = 12V, VBOOST = VSUPN = VSUPP = 15V, VON = 25V, VOFF = -8V, over temperature from -40C to +105C, unless otherwise stated. (Continued) DESCRIPTION POUT Charge Pump Short Detection NOUT Charge Pump Short Detection CONDITIONS V(FBP) falling less than V(FBN) rising more than MIN TYP 0.9 0.4 MAX UNIT V V
VON Slice POSITIVE SUPPLY = V(POUT) I(POUT)_slice VON Slice Current from POUT Supply CTL = VDD, sequence complete CTL = AGND, sequence complete RON (POUT-COM) RON (DRN-COM) RON_COM PROT IPROT_ON PROT Pull-Down Current or Resistance VPROT > 0.9V when Enabled by the Start-U VPROT < 0.9V PROT Pull-Up Current when Disabled VPROT < 20V 38 500 2 50 760 3 60 1000 4 A mA ON Resistance between POUT-COM ON Resistance between DRN-COM ON Resistance between DRN-COM and PGND CTL = VDD, sequence complete CTL = AGND, sequence complete 200 400 150 5 30 260 500 200 10 60 400 A A
IPROT_OFF
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ISL97653A Typical Application Diagrams
VIN M0 R22 75k C1 2.2F 34 COMP C2 R2 4.7nF 0 PGND1 PGND2 HVS EN PROT C1P C4 220nF C1N C2P C5 220nF C2N CTL C6 0.22F CDEL 30 32 33 27 26 36 15 16 17 18 24 25 VON SLICE 22 PGND5 14 12 10 INTERNAL REGULATOR VOFF CP 11 SUPN VREF FBN R11 40k R12 328k VOFF D2 D3 L L2 6.8H R13 2k C14 20F C12 470nF VLOGIC C19 220nF COM VON CP 20 SEQUENCING/FAULT CONTROL 19 21 SUPP POUT R6 983k FBP R7, 50k R10 15 C22 0.1F R8 1k R9 1k C9 470nF VON HVS 28 RSET R4 5k R5 20k BOOST 35 29 LX2 FBB LX1 L L1 6.8H D1 AVDD C3 22F x3 R3 55k
C30 Optional R21 75k
23
DRN
R17 100k
VL C7 4.7F
9
13 PVIN1 PVIN2 C0 10F C8 4.7nF CM2 R20 10k PGND3 PGND4 5 6 38 1 7 BUCK 3 4 8 2
NOUT CB C11 220nF C13 1F D4
LXL1 LXL2 FBL VLOGIC
R14 1.2k R17 Q1 R15 5.4k
VLOGIC2 C15 4.7F
40 LDO CONTROLLER AGND 39 31 TEMP SENSOR
LDO-CTL LDO-FB TEMP C16 10nF
37
R16 5k
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ISL97653A Typical Application Diagrams (Continued)
RSET HVS VREF PROT
CM1 GM AMPLIFIER FBB VREF UVLO COMPARATOR + +
HVS LOGIC
SAWTOOTH GENERATOR SLOPE COMPENSATION LX1 LX2
BUFFER
CONTROL LOGIC
RSENSE 0.75 VREF FREQ VL PVIN1,2 CURRENT LIMIT COMPARATOR CURRENT LIMIT THRESHOLD 680kHz OSCILLATOR CURRENT AMPLIFIER PGND1 PGND2
REGULATOR REFERENCE BIAS AND SEQUENCE CONTROLLER
CDEL EN
VL PVIN1,2 SUPN LXL1 LXL2 CONTROL LOGIC CURRENT LIMIT COMPARATOR + CURRENT LIMIT THRESHOLD BUFFER CURRENT AMPLIFIER GM AMPLIFIER CM2 FBL VREF CB
NOUT
FBN 0.2V
+
SLOPE COMPENSATION SAWTOOTH GENERATOR
+
UVLO COMPARATOR + 0.4V 0.75 VREF +
LDO CONTROL LOGIC2
LDO-CTL LDO-FB
FBP VREF
+
SUPP
TEMP SENSOR
TEMP
POUT SUPP
C1-
C1+
POUT
C2+
C2-
DRN
CTL
COM
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ISL97653A Typical Performance Curves
100 LOAD REGULATION (%) 0.5 0.4 0.3 VIN = 5V 0.2 0.1 0.0 0 500 IO (mA) 1000 1500 VIN = 12V VIN = 8V
EFFICIENCY (%)
90 VIN = 5V 80 VIN = 8V
VIN = 12V
70
0
500 IO (mA)
1000
1500
FIGURE 1. BOOST EFFICIENCY
FIGURE 2. BOOST LOAD REGULATION
0.08 LINE REGULATION (%) 0.06 0.04 0.02 0.00 -0.02 -0.04 5 IO = 400mA 6 7 8 9 10 11 12 13 14 EFFICIENCY (%) IO = 100mA
100 VIN = 5V 90 80 VIN = 8V 70 60 50 VIN = 12V
0
500
1000 IO (mA)
1500
2000
VIN (V)
FIGURE 3. BOOST LINE REGULATION
FIGURE 4. BUCK EFFICIENCY
0.3 LOAD REGULATION (%) LINE REGULATION (%) 0.2 0.1 0.0 -0.1 -0.2 -0.3 VIN = 8V 0 500 1000 IO (mA) 1500 2000 VIN = 12V VIN = 5V
0.10 0.08 IO = 400mA 0.06 0.04 0.02 0.00 IO = 100mA
5
6
7
8
9
10
11
12
13
14
VIN (V)
FIGURE 5. BUCK LOAD REGULATION
FIGURE 6. BUCK LINE REGULATION
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ISL97653A Typical Performance Curves (Continued)
0 LOAD REGULATION (%) -1 -2 -3 -4 -5 VON = 25V LOAD REGULATION (%) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 0 10 VON = 25V 20 30 ION (mA) 40 50 60
0
10
20
30 ION (mA)
40
50
60
FIGURE 7. VON LOAD REGULATION
FIGURE 8. VOFF LOAD REGULATION
CH1 = AVDD (VBOOST)(500mV/DIV) CH2 = IO (BOOST)(200mA/DIV)
0.0 LOAD REGULATION (%) -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 ILDO (mA) 1ms/DIV VLOGIC = 2.3V
FIGURE 9. LOGIC LDO LOAD REGULATION
FIGURE 10. BOOST TRANSIENT RESPONSE
CH1 = AVDD (VBOOST) (100mV/DIV) CH2 = IO (BOOST) (100mA/DIV)
CH1 = VCTL (5V/DIV) CH2 = COM (10V/DIV)
1ms/DIV
40s/DIV
FIGURE 11. BUCK TRANSIENT RESPONSE
FIGURE 12. VON SLICE OPERATION
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ISL97653A Typical Performance Curves (Continued)
Ch1 = LXL (400ns/DIV) Ch2 = ILXL (400ns/DIV) Ch1 = LXL (400ns/DIV) Ch2 = ILXL (400ns/DIV)
FIGURE 13. BOOST CURRENT LIMIT
FIGURE 14. BUCK CURRENT LIMIT
Pin Descriptions
PIN NUMBER 1 2 3, 4 5, 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME PVIN2 CB LXL1, 2 PGND3,4 CM2 FBL VL VREF FBN SUPN NOUT PGND5 C1P C1N C2P C2N SUPP FBP POUT COM DRN CTL DESCRIPTION Logic buck supply voltage. This is also the analog supply from which the VL is generated. Needs at least 1F bypassing. Logic buck boot strap pin. Generate the gate drive voltage for the N-Channel MOSFET by connecting a 1F cap to the switching node LXL1,2. Logic buck switching node. Source of the high side internal power N-Channel MOSFET for the Buck. Logic buck ground pin. Buck compensation pin. An RC network is recommended. Increase R for better transient response at the expense of stability. Logic buck feedback pin. High impedance input to regulate at 1.215V. 5.25V internal regulator output. Bypass with a 4.7F cap. Ref voltage is generated from VL. Reference voltage output. Bypass with a low valued cap for transients - recommend 220nF. Should not be greater than 5 times CDEL cap to ensure correct start-up sequence. Negative charge pump feedback pin. High impedance input to regulate to 0.203V. Negative charge pump supply voltage. Can be the same as or different from AVDD. Negative charge pump driver output. Charge pump ground pin. Charge pump capacitor 1, positive connection. Charge pump capacitor 1, negative connection. Charge pump capacitor 2, positive connection. Charge pump capacitor 2, negative connection. Positive charge pump supply. Can be the same as or different from AVDD. Positive charge pump feedback pin. High impedance input to regulate at 1.215V VON charge pump output. High voltage switch control output. VON slice output. Lower reference voltage for VON slice output. Usually connected to AVDD. Input control pin for VON slice output.
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ISL97653A Pin Descriptions (Continued)
PIN NUMBER 25 26 27 28 29 30 31 32, 33 34, 35 36 37 38 39 40 PIN NAME CDEL EN HVS RSET FBB COMP TEMP PGND1, 2 LX1, 2 PROT AGND PVIN1 LDO-FB LDO-CTL DESCRIPTION VON slice control delay input. Minimum 47nF. Recommend 220nF but is only limited by leakage in the cap reaching A levels. Chip enable (active high). Can be driven to VIN levels. High-voltage stress input select pin. High selects high voltage mode. Voltage set pin for HVS test. RSET connects to ground in the high voltage mode - RSET high. AVDD boost feedback pin. High impedance input to regulate at 1.215V. Boost compensation network pin. An RC network is recommended. Increase R for better transient response at the expense of stability. An R = 0 is recommended for 4.4A Boost requirements. Temperature sensor output voltage. An analog voltage from 0V to 3V for temperatures of -40C to +150C. Boost ground pins. Boost switch output. Drain of the internal power NMOS for the Boost. Gate driver of the Input protection switch. Goes low when EN is high. Can be used to modulate the passive input inrush current as shown by R21,R22, and C30 in the typical application diagram. Analog ground. Separate from PGND's and star under the chip. Logic buck supply voltage.This is also the analog supply from which the VL is generated. Needs at least 1F bypassing. LDO controller feedback. High impedance input to regulate at 1.215V. LDO control pin. Gate drive for the external PNP BJT.
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ISL97653A Application Information
AVDD Boost Converter
The AVDD boost converter features a fully integrated 4.4A boost FET. The regulator uses a current mode PI control scheme which provides good line regulation and good transient response. It can operate in both discontinuous conduction mode (DCM) at light loads and continuous mode (CCM). In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by Equation 1:
V boost 1 ----------------- = -----------1-D V IN (EQ. 1)
Table 1 gives typical values (worst case margins are considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, FSWand IOMAX):
TABLE 1. MAXIMUM OUTPUT CURRENT CALCULATION VIN (V) 5 5 5 12 12 VO (V) 9 12 15 15 18 L (H) 6.8 6.8 6.8 6.8 6.8 IOMAX (mA) 2215 1673 1344 3254 2670
where D is the duty cycle of the switching MOSFET. The boost soft-start function is digitally controlled within a fixed 10ms time frame during which the current limit is increased in eight linear steps. The boost converter uses a summing amplifier architecture for voltage feedback, current feedback, and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is triggered. Since this comparison is cycle based, the PWM output will be released after the peak current goes below the current limit threshold. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60k is recommended. The boost converter output voltage is determined by Equation 2:
R3 + R4 A VDD = -------------------- x V FBB R4 (EQ. 2)
Boost Converter Input Capacitor
An input capacitor is used to suppress the voltage ripple injected into the boost converter. A ceramic capacitor with capacitance larger than 10F is recommended. The voltage rating of input capacitor should be larger than the maximum input voltage. Some capacitors are recommended in Table 2 for input capacitor.
TABLE 2. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION CAPACITOR 10F/25V 10F/25V SIZE 1210 1210 VENDOR TDK Murata PART NUMBER C3225X7R1E106M GRM32DR61E106K
Boost Inductor
The boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. Values of 3.3H to 10H are recommended to match the internal slope compensation as well as to maintain a good transient response performance. The inductor must be able to handle the average and peak currents expressed in Equations 5 and 6:
IO I LAVG = -----------1-D I L I LPK = I LAVG + -------2 (EQ. 5) (EQ. 6)
where R3 and R4 are in the "" on page 5. Unless otherwise stated, component variables referred to in equations refer to the Typical Application Diagram. The current through the MOSFET is limited to 4.4A peak. This restricts the maximum output current (average) based on Equation 3:
I L V IN I OMAX = I LMT - -------- x -------- V 2 O (EQ. 3)
Some inductors are recommended in Table 3.
TABLE 3. BOOST INDUCTOR RECOMMENDATION INDUCTOR 10H/ 5.1APEAK 5.9H/ 6APEAK DIMENSIONS (mm) VENDOR 13x13x4.5 TDK PART NUMBER RLF12545T-100M5R1 CDEP12D38NP-5R9MB-120
Where IL is peak to peak inductor ripple current, and is set by Equation 4. fs is the switching frequency (680kHz).
V IN D I L = --------- x ---L fS (EQ. 4)
12.9X12.9X4 Sumida
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Rectifier Diode (Boost Converter)
A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The reverse voltage rating of this diode should be higher than the maximum output voltage. The rectifier diode must meet the output current and peak inductor current requirements. The following table lists two recommendations for boost converter diode.
TABLE 4. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION DIODE FYD0504SA 30WQ04FN VR/IAVG RATING 50V/2A 40V/3.5A PACKAGE DPAK DPAK VENDOR Fairchild Semiconductor International Rectifier
LX1, LX2 FBB INTERSIL ISL97653A
Stability can be examined by repeatedly changing the load between 100mA and a max level that is likely to be used in the system being used. The AVDD voltage should be examined with an oscilloscope set to AC 100mV/DIV and the amount of ringing observed when the load current changes. Reduce excessive ringing by reducing the value of the resistor in series with the CM1 pin capacitor.
Cascaded MOSFET Application
A 20V N-Channel MOSFET is integrated in the boost regulator. For applications requiring output voltages greater than 20V, an external cascaded MOSFET is needed as shown in Figure 15. The voltage rating of the external MOSFET should be greater than AVDD.
VIN AVDD
Output Capacitor
Integrating output capacitors supply the load directly and reduce the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor.
V O - V IN IO -1 V RIPPLE = I LPK x ESR + ----------------------- x --------------- x --V C f
O OUT s
(EQ. 7)
FIGURE 15. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS
For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. Note: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. COUT in Equation 7 assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at zero volts. Table 5 shows some selections of output capacitors.
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION CAPACITOR 10F/25V 10F/25V SIZE 1210 1210 VENDOR TDK Murata PART NUMBER C3225X7R1E106M GRM32DR61E106K
VIN Protection
A series external P-FET can be used to prevent passive power-up inrush current from the Boost output caps charging to VIN - VSCHOTTKY via the boost inductor and Schottky diode. This FET also adds protection in the event of a short circuit on AVDD. The gate of the PFET (shown as M0 in the "" on page 5) is controlled by PROT. When EN is low, PROT is pulled internally to PVIN1, thus M0 is switched off. When EN goes high, PROT is pulled down slowly via a 50A current source, switching M0 on. If the device is powered up with EN tied to high, M0 will remain switched off until the voltage on VL exceeds the VLOR threshold. Once the voltage on PROT falls below 0.6V and the step-up regulator is within 90% of its target voltage, PROT is pulled down to ground via a 1.3k impedance. If AVDD falls 10% below regulation, the drive to PROT reverts to a 50A current source. If a timed fault is detected, M0 is actively switched off. Several additional external components can optionally be used to fine-tune the function of pin PROT (shown in the dashed box near M0 in application diagram). PROT ramp rate can be controlled by adding a capacitor C30 between gate and source of M0. M0 gate voltage can be limited during soft-start by adding a resistor (~75k) between gate
PI Loop Compensation (Boost Converter)
The boost converter of ISL97653A can be compensated by a RC network connected from COMP pin to ground. C2 = 4.7nF and R2 = 0 to 10. A RC network is used in the demo board. A higher capacitor value can be used to increase system stability.
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and source of M0. In addition, a resistor can be connected between PROT and the gate of M0, in order to limit the maximum VGS of M0 at all times. Where Io is the output current of the buck converter. Table 6 shows some recommendations for input capacitor.
TABLE 6. INPUT CAPACITOR (BUCK) RECOMMENDATION CAPACITOR 10F/16V 10F/10V 22F/16V SIZE 1206 0805 1210 TDK Murata Murata VENDOR PART NUMBER C3216X7R1C106M GRM21BR61A106K C3225X7R1C226M
Buck Converter
The buck converter is a step down converter supplying power to the logic circuit of the LCD system. The ISL97653A integrates a high voltage N-channel MOSFET to save cost and reduce external component count. In the continuous current mode, the relationship between input voltage and output voltage as expressed in Equation 8:
V LOGIC --------------------- = D V IN (EQ. 8)
Buck Inductor
A 3.3H to 10H inductor range is recommended for the buck converter. Besides the inductance, the DC resistance and the saturation current are also factors that need to be considered when choosing a buck inductor. Low DC resistance can help maintain high efficiency. Saturation current rating should be higher than 2A. Here are some recommendations for buck inductor.
TABLE 7. BUCK INDUCTOR RECOMMENDATION INDUCTOR 4.7H/ 2.7APEAK 6.8H/ 3APEAK DIMENSIONS (mm) 5.7x5.0x4.7 7.3x6.8x3.2 VENDOR Murata TDK PART NUMBER LQH55DN4R7M01K RLF7030T-6R8M2R8
Where D is the duty cycle of the switching MOSFET. Because D is always less than 1, the output voltage of a buck converter is lower than input voltage. The peak current limit of buck converter is set to 2.5A, which restricts the maximum output current (average) based on Equation 9:
I OMAX = 2.5A - I P-P (EQ. 9)
Where IP-P is the ripple current in the buck inductor as shown in Equation 10:
V LOGIC I pp = --------------------- ( 1 - D ) L fs (EQ. 10)
Rectifier Diode (Buck Converter)
A Schottky diode is recommended for fast recovery and low forward voltage. The reverse voltage rating should be higher than the maximum input voltage. The peak current rating is 2.5A, and the average current is given by Equation 13:
I avg = ( 1 - D )*I o (EQ. 13)
Where L is the buck inductor, fs is the switching frequency (680kHz).
Feedback Resistors
The buck converter output voltage is determined by Equation 11:
R 14 + R 13 V LOGIC = -------------------------- x V FBL R 14 (EQ. 11)
Where Io is the output current of buck converter. The following table shows some diode recommended.
TABLE 8. BUCK RECTIFIER DIODE RECOMMENDATION DIODE PMEG2020EJ SS22 VR/IAVG RATING 20V/2A 20V/2A PACKAGE SOD323F SMB VENDOR Philips Semiconductors Fairchild Semiconductor
Where R13 and R14 are the feedback resistors in the buck converter loop to set the output voltage Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 1k is recommended.
Buck Converter Input Capacitor
Input capacitance should support the maximum AC RMS current which occurs at D = 0.5 and maximum output current.
I acrms ( C IN ) = D ( 1 - D ) IO (EQ. 12)
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Output Capacitor (Buck Converter)
Four 10F or two 22F ceramic capacitors are recommended for this part. The overshoot and undershoot will be reduced with more capacitance, but the recovery time will be longer.
TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION CAPACITOR 10F/6.3V 10F/6.3V 22F/6.3V 100F/6.3V SIZE 0805 0805 1210 1206 VENDOR TDK Murata TDK Murata PART NUMBER C2012X5R0J106M GRM21BR60J106K C3216X5R0J226M GRM31CR60J107M
Positive Charge Pump Design Consideration
All positive charge pump diodes (D1, D2 and D3 shown in the "NEGATIVE CHARGE PUMP BLOCK DIAGRAM" on page 16) for x2 (doubler) and x3 (Tripler) modes of operation are included in the ISL97653A. During the chip start-up sequence the mode of operation is automatically detected when the charge pump is enabled. With both C7 and C8 present, the x3 mode of operation is detected. With C7 present, C8 open and with C1+ shorted to C2+, the x2 mode of operation will be detected. Internal switches M1, M2 and M3 isolate POUT from SUPP until the charge pump is enabled. This is important for TFT applications that require the negative charge pump output (VOFF) and AVDD supplies to be established prior to POUT. The maximum POUT charge pump current can be estimated from the following equations assuming a 50% switching duty:
I MAX ( 2x ) min of 40mA or 2 * V SUPP - 2 * V DIODE ( 2 * I MAX ) - V ( V ON ) ------------------------------------------------------------------------------------------------------------------------- * 0.95A ( 2 * ( 2 * R ONH + R ONL ) ) I MAX ( 3x ) min of 40mA or 3*V * - 3 * V DIODE ( 2 * I MAX ) - V ( V ON ) SUP P ------------------------------------------------------------------------------------------------------------------------- * 0.95V ( 2 * ( 3 * R ONH + 2 * R ONL ) ) (EQ. 14)
PI Loop Compensation (Buck Converter)
The buck converter of ISL97653A can be compensated by a RC network connected from CM2 pin to ground. C8 = 4.7nF and R20 = 10k RC network is used in the demo board. A larger value resistor can lower the transient overshoot, however, at the expense of stability of the loop. The stability can be optimized in a similar manner to that described in "PI Loop Compensation (Boost Converter)" on page 12.
Bootstrap Capacitor (C13)
This capacitor provides the supply to the high driver circuitry for the buck MOSFET. The bootstrap supply is formed by an internal diode and capacitor combination. A 1F is recommended for ISL97653A. A low value capacitor can lead to overcharging and in turn damage the part. During very light loads, the on-time of the low side diode may be insufficient to replenish the bootstrap capacitor voltage. Additionally, if VIN - VBUCK < 1.5V, the internal MOSFET pull-up device may be unable to turn-on until VLOGIC falls. Hence, there is a minimum load requirement in this case. The minimum load can be adjusted by the feedback resistors to FBL.
Note: VDIODE (2 * IMAX) is the on-chip diode voltage as a function of IMAX and VDIODE (40mA) < 0.7V.
Charge Pump Controllers (VON and VOFF)
The ISL97653A includes 2 independent charge pumps (see charge pump block and connection diagram). The negative charge pump inverts the SUPN voltage and provides a regulated negative output voltage. The positive charge pump doubles or triples the SUPP voltage and provides a regulated positive output voltage. The regulation of both the negative and positive charge pumps is controlled by internal comparators that sense the output voltage. These sensed voltages are then compared to scaled internal reference voltages. Charge pumps use pulse width modulation to adjust the pump period, depending on the load present. The pumps can provide 100mA for VOFF and 40mA for VON.
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SUPP M2 C1C7 C1+ SUPP M1 External Connections and Components x2 Mode x3 Mode Both
M4
Control 680KHz 0.9V
D3
D2
D1
POUT C14
SUPP Error M3 VREF FB
C2+ C8 C2C21 R8
M5
FBP
C22
R9
FIGURE 16. VON FUNCTION DIAGRAM
In voltage doubler configuration, the maximum VON is as given by the following equation:
V ON_MAX(2x) = 2 * ( V SUPP - V DIODE ) - 2 * I OUT * ( 2 * R ONH + R ONL ) (EQ. 15)
The maximum VOFF output voltage of a single stage charge pump is:
V OFF_MAX ( 2x ) = - V SUPP + V DIODE + 2 * I OUT * ( R ON ( NOUT )H + R ON ( NOUT )L ) (EQ. 18)
For Voltage Tripler:
VON_MAX(3x) = 3 * ( V SUPP - V DIODE ) - 2 * I OUT * ( 3 * R ONH + 2 * RONL (EQ. 16)
R6 and R7 in the Typical Application Diagram determine VOFF output voltage.
R7 R7 V OFF = V FBN * 1 + ------- - V REF * ------- R6 R6 (EQ. 19)
VON output voltage is determined by the following equation:
R 8 V ON = V FBP * 1 + ------ R 9 (EQ. 17)
*Although in the given typical application diagram, SUPP and SUPN are connected to AVDD, depending on a specific application, SUPN and/or SUPP could be connected to either AVDD or VIN.
Negative Charge Pump Design Consideration
The negative charge pump consists of an internal switcher M1, M2 which drives external steering diodes D2 and D3 via a pump capacitor (C12) to generate the negative VOFF supply. An internal comparator (A1) senses the feedback voltage on FBN and turns on M1 for a period up to half a CLK period to maintain V(FBN) in regulated operation at 0.2V. External feedback resistor R6 is referenced to VREF. Faults on VOFF which cause VFBN to rise to more than 0.4V, are detected by comparator (A2) and cause the fault detection system to start the internal fault timer which will cause the chip to power down if the fault persists.
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VREF A2 FAULT 0.4V FBN A1 0.2V VDD SUPN C20 820pF R6 40k R7 328k C19 100pF
1.2MHz
STOP
M2 C12 220nF D2 VOFF (-8V) D3 C13 470nF
CLK NOUT
EN
PWM CONTROL
M1 PGND
FIGURE 17. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
VON Slice Circuit
The VON slice circuit functions as a three way multiplexer, switching the voltage on COM between ground, DRN and POUT, under control of the start-up sequence and the CTL pin. During the start-up sequence, COM is pulled to ground via an NDMOS FET with RDS(on) of 260 ohms. After the start-up sequence has completed, CTL is enabled and acts as a multiplexer control such that if CTL is low, COM connects to DRN through a 30 internal MOSFET, and if CTL is high, COM connects to POUT internally via a 5 MOSFET. The slew rate of the switch control circuit is mainly restricted by the load capacitance at COM pin and is given by Equation 20:
Vg V ------- = -----------------------------------|| R ) x C t ( Ri L L (EQ. 20)
VLOGIC2 LDO
An LDO controller is also integrated to provide a second logic supply. The LDO-CTL pin drives the base of an external transistor which should be sized for the current required. A resistor divider is used to set the output voltage by feeding back a reference voltage to LDO-FB. The internal feedback reference is 1.215V.
HVS Operation
When the HVS input is taken high, the ISL97653A enters HVS test mode. In this mode, the output of AVDD is increased by switching RSET to ground, and the AVDD is set to:
R3 + Rx A VDD = -------------------- x V FBB Rx (EQ. 22)
Where Vg is the supply voltage applied to DRN or voltage at POUT, which range is from 0V to 30V. Ri is the resistance between COM and DRN or POUT including the internal MOSFET rDS(on), the trace resistance and the resistor inserted, RL is the load resistance of VON slice circuit, and CL is the load capacitance of switch control circuit. In the Typical Application Circuit, R8, R9 and C22 give the bias to DRN based on Equation 21:
V ON R 9 +AVDD R 8 V DRN = -------------------------------------------------------R9 + R
8
Where Rx is the value of R4 in parallel with R5. AVDD voltage higher than the maximum rating of the boost MOSFET may damage the part.
Fault Protection
The ISL97653A incorporates a number of fault protection schemes. AVDD, VON, and VOFF are constantly monitored. If fault conditions are detected for longer than 1ms on these FB inputs, the device stops switching and the outputs are disconnected. The ISL97653A also integrates over temp and over current protection.
(EQ. 21)
Supply Sequencing
When the input voltage VIN is higher than 4V(UVLO), VREF, VLOGIC, and VLOGIC2 are turned on. VLOGIC has a 9ms fixed soft-start at start-up. AVDD, VON, and VOFF are dependant on the EN pin.
And R10 can be adjusted to adjust the slew rate.
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When EN is taken high, voltage of pin PROT and VOFF start ramping down. Once the PROT voltage falls below 0.9V, AVDD starts up with a 9ms fixed soft-start time. Please note if VOFF is to start earlier than AVDD, then the SUPN needs to connect to Vin, and Vin voltage should be larger than VOFF absolute value. The delay between VOFF and AVDD can be controlled by C30 in the typical application diagram and is given by Equation 23:
T DELAY = ( V IN - 0.9V ) x C 30 ( 50A ) (EQ. 23)
Fault Sequencing
The ISL97653A has advanced overall fault detection systems including Over Current Protection (OCP) for both boost and buck converters, Under Voltage Lockout Protection (UVLP) and Over-Temperature Protection. Once the peak current flowing through the switching MOSFET of the boost and buck converters triggers the current limit threshold, the PWM comparator will disable the output, cycle by cycle, until the current is back to normal.
The successful completion of the AVDD soft-start cycle triggers two simultaneous events. VON begins to ramp up and the voltage on CDEL starts ramping up. When the voltage reaches 1.215V, VON slice starts.
Layout Recommendation
The device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. There are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VREF and VL bypass capacitors close to the pins. 3. Reduce the loop with large AC amplitudes and fast slew rate. 4. The feedback network should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point. 6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. Minimize feedback input track lengths to avoid switching noise pick-up. A demo board is available to illustrate the proper layout implementation.
VIN VREF VLOGIC EN PROT AVDD VON VOFF 2.8V CDEL VON Slice * For demonstration only, not to scale 1.215V 0.9V
FIGURE 18.
Temperature Sensor
The ISL97653A also includes a temperature output for use in system thermal management control. The integrated sensor measures the die temperature over the -40C to +150C range. Output is in the form of an analog voltage on the TEMP pin in the range of 0V to 3V, which is proportional to the sensed die temperature. Temperature accuracy is 8.5C over the -40C to +150C temperature range. The device should be disabled by the user when the TEMP pin output reaches 3V ( = +150C die junction). Operation of the device between +125C and +150C can be tolerated for short periods, however in order to maximize the life of the IC, it is recommended that the effective continuous operating junction temperature of the die should not exceed +125C.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 17
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Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06
4X 4.5 6.00 A B 6 PIN 1 INDEX AREA 31 30 36X 0.50 40 1 6 PIN #1 INDEX AREA
4 . 10 0 . 15 6.00
21 (4X) 0.15 20 TOP VIEW 40X 0 . 4 0 . 1 BOTTOM VIEW 11
10
0.10 M C A B 4 0 . 23 +0 . 07 / -0 . 05
SEE DETAIL "X" 0.10 C BASE PLANE SIDE VIEW ( 36X 0 . 5 ) SEATING PLANE 0.08 C C
0 . 90 0 . 1 ( 5 . 8 TYP ) ( 4 . 10 )
C ( 40X 0 . 23 ) ( 40X 0 . 6 ) TYPICAL RECOMMENDED LAND PATTERN
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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